Ion implantation is a standard technique for introducing impurities into substrates. During an ion implantation process, a desired impurity material is typically ionized in an ion source, the resultant ions are accelerated to form an ion beam of prescribed energy, and the ion beam is then directed at a surface of a substrate, such as a silicon wafer. Constituent ions in the ion beam may be referred to as “beam ions” or “dopant ions.”
The beam ions typically penetrate into the target substrate and lose energy by interacting with electrons in the substrate (a mechanism known as “electronic stopping”) or by undergoing collisions with the substrate nuclei (a mechanism known as “nuclear stopping”). Electronic stopping can be analogized to a viscous drag on the ions, and does not lead to permanent damages to the substrate's crystal lattice. In contrast, nuclear stopping may lead to the displacement of a substrate atom, leaving a vacancy in the lattice. The displaced atom may become an interstitial, i.e., located at a site between lattice positions of atoms in the substrate's crystal structure. A vacancy-interstitial pair formed when an atom is displaced from a lattice site to an interstitial site is referred to as a “Frenkel pair.” One beam ion may undergo many nuclear collisions, and the resulting displaced atoms may themselves have enough energy to undergo their own nuclear collisions and create further displaced atoms, which phenomenon is known as “collision cascade.”
When the beam ions and all the displaced atoms have come to a rest, the crystal structure of the substrate will contain primary damages, consisting of vacancies and interstitials. The interstitials tend to be knocked deeper into the substrate by the beam ion collisions, and so the damage associated with the interstitials accumulates at ranges associated with the deepest depth (end of range) attained by the dopant ions. The extent of primary damages formed depends on various characteristics of the ion beam, such as beam energy, ion mass, total implanted dose, and implanted dose rate, and on characteristics of the substrate such as atomic composition, mass and crystal orientation with respect to the ion beam.
Once formed, interstitials and vacancies can diffuse through the substrate. If a vacancy and an interstitial interact, they may recombine, reverting to the original crystal lattice. Alternatively, a vacancy and an interstitial can recombine in such a way as to leave a defect in the lattice. If multiple vacancies, or interstitials, interact with each other, they may form other stable, secondary damage structures. If the damage in a region of the lattice reaches a critical density, the crystal converts into a metastable state, known as amorphous silicon. The diffusivity of the vacancies and interstitials, and therefore rate of damage repair during the ion implantation, are often enhanced as the substrate temperature increases. Substrate temperature is therefore an important parameter that may influence the amount and characteristics of damage remaining after an ion implantation process.
Low-temperature ion implantation has been investigated as a technique for achieving ultra-shallow junctions needed in modern complementary metal-oxide-semiconductor (CMOS) devices. Most low-temperature ion implantation approaches so far have focused on a simplistic goal of lowering wafer temperature as much as possible. There has not been any serious attempt to closely monitor or precisely control wafer temperatures during ion implantation. It is generally considered sufficient if the wafer temperature is below some preset upper limit.
In a production environment it is important that each process step has reproducible results. This applies to the same process (or recipe) carried out over time on a single ion implanter and to the same process carried out on two or more different ion implanters. Until now, controlling parameters such as beam energy, beam current, and beam current density have been sufficient to keep tight enough tolerances on device performance. Wafer temperature and wafer temperature profile have not been treated as critical process parameters. As the critical dimensions of CMOS devices grow smaller, tighter control of ion implantation processes are demanded.
In view of the foregoing, it would be desirable to provide a solution for temperature-controlled ion implantation which overcomes the above-described inadequacies and shortcomings.